Japanese Laid-Open Patent Application No. 7-22510 discloses a semiconductor integrated circuit device capable of facilitating the layout and disposing power source wiring and electrodes by repeatedly disposing power supply block cells. Specifically, a CCB bump (a power source electrode) is disposed at the center of power supply block cells, and CCB bumps for signals are disposed at the four corners. That is, both the CCB bump and the CCB bumps for signals are orderly disposed on the principal surface of semiconductor chips in such a manner that the consistency is maintained with the layout of the basic cells. When preparing the basic cell, a basic circuit region having a plurality of MIS.FETs required for forming one basic circuit is prepared, and a plurality of regions are laid out in mirror symmetry with a predetermined power supply wiring disposed above the basic cell as a border. By doing this, the disposing and laying out of semiconductor elements forming the basic cell can be performed more easily, man-hours for laying and disposing can be reduced thereby shortening the laying and disposing time.
Further, Japanese Laid-Open Patent Applications No. 11-250700 discloses a memory mixed semiconductor integrated circuit device in which a test circuit for operating the efficient test of a large-scaled memory macro by a few terminals for test is incorporated. Specifically, a memory macro is mixed with a logic part, and provided with a test circuit for decoding a coded input signal for test supplied to an input terminal for test for testing the memory macro, and test-operating the memory macro without the logic part. The test circuit is provided with a signal generating circuit for decoding a coded memory control signal among input signals, and selectively performing direct access to the memory macro according to the memory control signal and non-coded address signal and data signal for executing the test operation, and a control circuit for decoding a coded memory macro activation signal and a memory macro selection signal among input signals for test, and selectively activating the signal generating circuit.